Emmanuel-Roy/RISC-V-RV32I-CPU_Verilog-Implementation

Implementation of the RV32I Instruction Set in Verilog.

RISC-V RV32I CPU - Verilog Implementation

Introduction:

After taking ECE 316 (Digital Logic Design) at the University of Texas at Austin, I found that I enjoyed using HDLs. I thought it would be cool to make a CPU in Verilog, so after some research, I found the RISC-V RV32I ISA and got started.

This project required a ton of independent research, so there isn't much optimization. I plan to implement optimizations, such as parallelization and pipelining, after I develop those skills in ECE 460N (Computer Architecture) next spring.

Goals:

• Implement all of the RV32I's Base Instructions. ✅
• Create test benches to ensure maximum accuracy. ✅
• Synthesis on a Basys 3 with AMD Artix 7 FPGA Board.

Simulation Output (Basic Test Case)

Input: (Instructions.hex file)

Output:

Potential Plans:

• Implement Pipelining.
• Pass RISC-V rv32ui Unit Test..
• Implement Zicsr extension.
• Implement Zifencei extension.
• Run Linux

Reference:

• Blinker To RISC-V
• The RISC-V Instruction Set Manual
• How to Design a RISC-V Processor
• Writing a simple RISC-V emulator in plain C
• 16-Bit-CPU-using-Verilog
• Bare metal C on my RISC-V toy CPU
• RV32emu
• LupV
• RISCV
• Toast-RV32
• Jim Ledin “Modern Computer Architecture and Organization" (2022)
• David Patterson and John L. Hennessy "Computer Organization and Design RISC-V Edition: The Hardware Software Interface" (2nd Edition)