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EricZhang1412/ASIC_for_ML-in-Hardware
This repo stores original verilog-based codes for employing Fully-Connected Layer and 1-d Convolutional Layer into Xilinx Zynq 7000 SoC
VHDL
This repo stores original verilog-based codes for employing Fully-Connected Layer and 1-d Convolutional Layer into Xilinx Zynq 7000 SoC
VHDL
This repository is not active