Essenceia

Building one block at a time.

Austin

Pinned Repositories

AES
RTL implementaion of 128 bit Advanced Encryption Standard (AES) encyption algorithm
Language:C60
ethernet-physical-layer
RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
Language:Tcl16 1 05
ITCH
RTL implementation of the ITCH protocol decoder.
Language:Verilog14
low-latency-ethernet
RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.
Language:Verilog1612
MoldUPD64
RTL implementation of a MoldUPD64 receiver.
Language:Verilog4 1 01
Nasdaq-HFT-FPGA
RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.
Language:C24 2 011
NASDAQ_server_C_lib
Fake nasdaq server C library used in testing FPGA HFT project
Language:C2 1 03
stm32h750-dev-board
Small embedded dev board with an STM32H7 and a full J-link connector
31
Zeldy
Zeldy is a power monitoring system.
20
Zeldy_HW
Language:AGS Script20

Essenceia's Repositories

Essenceia/Nasdaq-HFT-FPGA
RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.
Language:C24 2 011
Essenceia/ethernet-physical-layer
RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
Language:Tcl16 1 05
Essenceia/low-latency-ethernet
RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.
Language:Verilog1612
Essenceia/AES
RTL implementaion of 128 bit Advanced Encryption Standard (AES) encyption algorithm
Language:C60
Essenceia/MoldUPD64
RTL implementation of a MoldUPD64 receiver.
Language:Verilog4 1 01
Essenceia/stm32h750-dev-board
Small embedded dev board with an STM32H7 and a full J-link connector
31
Essenceia/NASDAQ_server_C_lib
Fake nasdaq server C library used in testing FPGA HFT project
Language:C2 1 03
Essenceia/Zeldy
Zeldy is a power monitoring system.
20
Essenceia/Blake2
Blake2 RTL implementation
Language:Verilog1 1 00
Essenceia/CAM
Content Addressable Memory Experimentations
Language:Verilog10
Essenceia/ethernet_packet_C_lib
C library for creating network packages, wireshark compatible, primarily for testing network layer RTL.
Language:C12
Essenceia/ITCH
RTL implementation of the ITCH protocol decoder.
Language:Verilog14
Essenceia/Nasdaq_binaryfile_utils
Language:C11
Essenceia/SoupBinTCP
RTL implementation of SoupBinTCP version 3.0
Language:Verilog11
Essenceia/Dec
RTL for the randomx corevm's decoder, algorithm used by monero.
Language:VHDL01
Essenceia/essenceia.github.io
Portfolio website
Language:CSS
Essenceia/eurostat_gunplot
Collection of scripts for eurostat data extraction and ploting using gunplot
Language:Gnuplot2 0
Essenceia/formal_experiements
Formal verification experiments
Language:Verilog1
Essenceia/gcc_bug
GCC internal error found in version 13.2.1, bug report
Language:C++1 0
Essenceia/GHDL-Hello-World
Simple GHDL example with makefile
Language:VHDL
Essenceia/hello_custom_fpga_board
Simple design to get familiar with a new custom FPGA baord
Language:Tcl
Essenceia/OUCH_5.0_C_lib
Nasdaq OUCH 5.0 C libary
Language:C1 0
Essenceia/PCB_Buisness_Card
Essenceia/rtl_utils
Collection of rtl tricks
Language:Verilog1 0
Essenceia/switch_scripts
Switch utilities scripts for the D2020.
Language:Shell
Essenceia/tcp
RTL implementation of the a single socket TCP client
Language:Verilog1
Essenceia/TotalView_ITCH_5.0_C_lib
Small C library to handle itch messages
Language:C1 01
Essenceia/utils_C_lib
Generic C FIFO library.
Language:C
Essenceia/verilog-ethernet
Rework of the "verilog-ethernet" repo
Language:Verilog
Essenceia/VPI_utils_C_lib
VPI utils C lib, used for interfacing with iverilog and verilator VPI interface.
Language:C1