Pinned Repositories
byteman
Bitstream relocation and manipulation tool.
eFPGA---RTL-to-GDS-with-SKY130
This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
FABulator
Fabric generator and CAD tools graphical frontend
FABulous
Fabric generator and CAD tools.
FABulous-Sky---a-heterogeneous-FPGA-fabric-in-Skywater130
https://caravel-user-project.readthedocs.io
fos
FOS - FPGA Operating System
FPGAVirusScanner
Program to scan for malicious FPGA designs.
heichips25-workshop
HeiChips 2025 LibreLane Workshop
open_eFPGA_v2
zynq-ultrascale-readback-capture
This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the same task to Zynq UltraScale+ MPSoC with several noticeable differences.
FPGA-Research's Repositories
FPGA-Research/FABulous
Fabric generator and CAD tools.
FPGA-Research/fos
FOS - FPGA Operating System
FPGA-Research/byteman
Bitstream relocation and manipulation tool.
FPGA-Research/eFPGA---RTL-to-GDS-with-SKY130
This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
FPGA-Research/FPGAVirusScanner
Program to scan for malicious FPGA designs.
FPGA-Research/zynq-ultrascale-readback-capture
This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the same task to Zynq UltraScale+ MPSoC with several noticeable differences.
FPGA-Research/FABulator
Fabric generator and CAD tools graphical frontend
FPGA-Research/open_eFPGA_v2
FPGA-Research/heichips25-workshop
HeiChips 2025 LibreLane Workshop
FPGA-Research/FABulous-Sky---a-heterogeneous-FPGA-fabric-in-Skywater130
https://caravel-user-project.readthedocs.io
FPGA-Research/heichips25-tapeout
HeiChips 2025 Tapeout on IHP SG13G2 130nm process
FPGA-Research/OrkhestraFPGAStream
Private repository for accelerating DBMS SQL queries with FPGAs
FPGA-Research/FABulous_board
A PCB created for FABulous FPGAs, based on the caravel board.
FPGA-Research/OWAS
Development and integration of a comprehensive open-source ecosystem for the design of complex RISC-V System-on-Chip (SoC) architectures, featuring support for embedded FPGA technologies.
FPGA-Research/FABulous-SKY130
FPGA-Research/fuserisc
Dual RISC-V DISC with integrated eFPGA
FPGA-Research/heichips25-template
The template for the HeiChips 2025 hackathon
FPGA-Research/GoAhead
GoAhead
FPGA-Research/nextpnr-fabulous
a fork of nextpnr for use with old versions of FABulous (check the fabulous branch for relevant changes) - FABulous now works with upstream nextpnr
FPGA-Research/FABulous-demo-projects
A Collection of Demo Projects For Testing FABulous
FPGA-Research/FPGA_IGNITE_2024
FPGA-Research/heichips25-pcb
The official PCB for HeiChips 2025
FPGA-Research/XilinxTCL_utilities
FPGA-Research/FPGA-VS-Web
FPGA VIrus Scanner Web Application
FPGA-Research/nextpnr
a fork of nextpnr for use with old versions of FABulous (check the fabulous branch for relevant changes) - FABulous now works with upstream nextpnr
FPGA-Research/readdebugbitstream
FPGA-Research/yosys
Yosys Open SYnthesis Suite fork for use with old versions of FABulous (check the fabulous branch for relevant changes) - FABulous now works with upstream yosys
FPGA-Research/.github