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From the IP catalog, select Integrated Logic Analyser
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From Probe ports tab, create clkProp as probe0 and Btrig as probe1.
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Follow the steps - https://vhdlwhiz.com/using-ila-and-vio/ to create a debug ILA core.
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Open Vivado, go to File -> Project -> New
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Give Project name and specify project location.
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Select RTL Project(Deselect - Do not specify sources at this time, if selected)
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Add all '.v' files provided in this repository.
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Add '.xdc' file provided in this repository.
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Select Arty A7 board.
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Make sure top_level.v is selected as main file in sources.
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From IP Catalog, search ILA. In general options -> change number of probes to 2. In Probe_Ports, change only probe0 width to 32.
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Select Ok and Genrate ILA.
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From Program and Debug, select Generate Bitstream (top right corner shows the ongoing operation).
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Once finished, open Hardware Manager -> Open Target -> Auto Connect -> Program Device. It should show Digilent board, select this and program.
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From ILA's Status window, select Run Trigger for this ILA, it will required generate waveforms.