/E203_SOC_G2

We run the E203 based on Genesys2 ,and add some additional IP to develop a powerful system

Primary LanguageVerilog

E203_SOC_G2

We run the E203 based on Genesys2 ,and add some additional IP to develop a powerful system

u can get the mcs file in systemv2.zip

hbird-sdk-master.zip包含了Genesys2板级文件,在NucleiStudio导入该包可直接创建genesys2的development board,默认以rom方式烧录

now(2022.9.26) the rtl soc is in pic file

This project will continue to update and welcome to join us

9月 axi 问题已解决

整个工程文件会在完善和代码规范后上传~