GauravDhak
🔌 Electronics Engineer & VLSI Enthusiast 💡 | 🌌 Delving into the frontiers of scalable chip architectures |
India
Pinned Repositories
2-bit-Branch-Predictor-in-Verilog
This project implements a 2-bit branch predictor in Verilog. Branch prediction is a technique used in CPU instruction pipelines to guess the outcome of a conditional branch instruction to avoid pipeline stalls. The 2-bit predictor uses a saturating counter to improve prediction accuracy.
GauravDhak
LRU-Cache-Memory
An LRU (Least Recently Used) cache memory in Verilog is designed to store and manage frequently accessed data by implementing a replacement policy that evicts the least recently used entries, ensuring efficient utilization of cache space and improved access times.
Single-port-Random-Access-Memory-RAM-
Single port Random Access Memory (RAM)" typically refers to a type of memory module or chip where data can be read from or written to through a single port, meaning it can handle one data access operation at a time.
SPI-Master-Slave-Communication-System
Designed and implemented an SPI master module in Verilog for interfacing with multiple slave devices.
System-Design-Resource
This repository is a comprehensive collection of resources aimed at helping software engineers and system architects enhance their skills in system design.
GauravDhak's Repositories
GauravDhak/2-bit-Branch-Predictor-in-Verilog
This project implements a 2-bit branch predictor in Verilog. Branch prediction is a technique used in CPU instruction pipelines to guess the outcome of a conditional branch instruction to avoid pipeline stalls. The 2-bit predictor uses a saturating counter to improve prediction accuracy.
GauravDhak/LRU-Cache-Memory
An LRU (Least Recently Used) cache memory in Verilog is designed to store and manage frequently accessed data by implementing a replacement policy that evicts the least recently used entries, ensuring efficient utilization of cache space and improved access times.
GauravDhak/Single-port-Random-Access-Memory-RAM-
Single port Random Access Memory (RAM)" typically refers to a type of memory module or chip where data can be read from or written to through a single port, meaning it can handle one data access operation at a time.
GauravDhak/System-Design-Resource
This repository is a comprehensive collection of resources aimed at helping software engineers and system architects enhance their skills in system design.
GauravDhak/GauravDhak
GauravDhak/SPI-Master-Slave-Communication-System
Designed and implemented an SPI master module in Verilog for interfacing with multiple slave devices.