Pinned Repositories
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Cache
L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC
ComputerArchitectureLab
This repository is used to release the Labs of Computer Architecture Course from USTC
CourseDigitalIC
国科大高等数字集成电路分析与设计课程2022fall
DC_script
syn script for DC Compiler
DeepLearning-Basics
DeepLearning Basics
Giftwen
Config files for my GitHub profile.
git-tutorial
HDLBits-UCAS
NPU_on_FPGA
在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。
Giftwen's Repositories
Giftwen/CourseDigitalIC
国科大高等数字集成电路分析与设计课程2022fall
Giftwen/DC_script
syn script for DC Compiler
Giftwen/ComputerArchitectureLab
This repository is used to release the Labs of Computer Architecture Course from USTC
Giftwen/HDLBits-UCAS
Giftwen/NPU_on_FPGA
在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。
Giftwen/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Giftwen/Cache
L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC
Giftwen/DeepLearning-Basics
DeepLearning Basics
Giftwen/Giftwen
Config files for my GitHub profile.
Giftwen/git-tutorial
Giftwen/Hello-Word
Giftwen/Masimulator
A Visual RISC-V Simulator
Giftwen/NPUSoC
第四届全国大学生嵌入式比赛SoC
Giftwen/s2
Giftwen/SpinalHDLDemo
Demo Sources for Learning Spinal HDL
Giftwen/SpinalWorkshop
Labs to learn SpinalHDL
Giftwen/ucas_course_to_wakeup
基于barryZZJ / ucas_course_to_calendar把课表导入手机日历的脚本，添加了导入至wakeup课程表的csv文件生成方法
Giftwen/UltraMIPS_Cache
This repository belongs to UltraMIPS_NSCSCC, and consists of the development of pipeline Cache(ICache/DCache) and associated components for dual-issue cpu.
Giftwen/UltraMIPS_NSCSCC
UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
Giftwen/verilog-axi
Verilog AXI components for FPGA implementation
Giftwen/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
Giftwen/ysyx-pa
一生一芯云空间