Sargantana is a 64-bit processor based on RISC-V that implements the RV64G ISA. Sargantana features a highly optimized 7-stage pipeline implementing out-of-order write-back, register renaming, and a non-blocking memory pipeline. Sargantana achieves a 1.26 GHz frequency in the typical corner, and up to 1.69 GHz in the fast corner using 22nm FD-SOI commercial technology.
To perform RTL simulations and/or emulating the design, please refer to the core_tile repo.
This work is licensed under the Solderpad Hardware License v2.1.
For more information, check the LICENSE file.
The list of authors can be found in the CONTRIBUTORS.md file.
Víctor Soria-Pardos, Max Doblas, Guillem López-Paradís, Gerard Candón, Narcís Rodas, Xavier Carril, Pau Fontova-Musté, Neiel Leyva, Santiago Marco-Sola, and Miquel Moretó. "Sargantana: A 1 GHz+ in-order RISC-V processor with SIMD vector extensions in 22nm FD-SOI". 25th Euromicro, 2022.