University of Pittsburgh ADVANCED DIGITAL DESIGN 2024 Spring
- Design a generic 32 bit adder/subtractor using generic statement and for-generate statement.
- Write a testbench to fully test VHDL design, verify the functionality using the behavioral simulation.
- Design the ALU, per the diagram shown in the picture above.
- Create the top level ALU using structural-architecture VHDL code.
- Write a VHDL testbench to verify the functionality of the ALU, at least test each ALU operation once.
- Synthesize, Implement and Generate Bitstream for ALU, then write C/C++ testbench to fully verify the functionality of FPGA-configured design.
- Design the 32-bit Multiplier Unit, per the hardware algorithm above. Final top-level Multiplier Unit should have the following IO ports.
- Write a VHDL or Tcl Script testbench to verify the functionality of the Multiplier Unit, should test a wide range of cases.
- Synthesize, implement and generate bitstream for your Multiplier Unit, then write C/C++ testbench to fully verify the functionality of your FPGA-configured design. You should test a wide range of cases and include random testing. You will be needing more regmap registers for this lab, so make sure to configure and take notes of their numbers and bit-widths.