H-S-S-11/basic-uart-transciever
A uart reciever and transmitter microcontroller peripheral created for end of semester 1 design exercise for practice
SystemVerilogGPL-3.0
No issues in this repository yet.
A uart reciever and transmitter microcontroller peripheral created for end of semester 1 design exercise for practice
SystemVerilogGPL-3.0
No issues in this repository yet.