Pinned Repositories
Algorithm
Awesome-SGX-Open-Source
A curated list of open-source projects that help exploit Intel SGX technology
block-inclusivecache-sifive
boom-attacks
Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
chisel-IDEA-demo
Gem5
riscv-linux
RISC-V Linux Port
riscv-pk
H-Y-B's Repositories
H-Y-B/chisel-IDEA-demo
H-Y-B/Awesome-SGX-Open-Source
A curated list of open-source projects that help exploit Intel SGX technology
H-Y-B/block-inclusivecache-sifive
H-Y-B/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
H-Y-B/chisel-template
chisel and sbt
H-Y-B/Gem5
H-Y-B/riscv-linux
RISC-V Linux Port
H-Y-B/riscv-pk
H-Y-B/ChampSim
ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.
H-Y-B/elf
H-Y-B/linux
H-Y-B/linux-sgx
Intel SGX for Linux*
H-Y-B/linux-sgx-driver
Intel SGX Linux* Driver
H-Y-B/lombok-rs
Lombok port for Rust
H-Y-B/macrokata
Learn Macros In Rust
H-Y-B/minimal-diplomacy
Example of Chisel3 Diplomacy
H-Y-B/openenclave
SDK for developing enclaves
H-Y-B/opensbi
RISC-V Open Source Supervisor Binary Interface
H-Y-B/r-lombok-macros
r-lombok is a rust macros that automatically plugs into your editor and build tools
H-Y-B/rCore
Rust version of THU uCore OS. Linux compatible.
H-Y-B/riscv-hpmcounters
A simple utility for doing RISC-V HPM perf monitoring.
H-Y-B/riscv-tests
H-Y-B/riscvv-test
RISC-V vector and other assembly code examples
H-Y-B/rocket-chip
Rocket Chip Generator
H-Y-B/SecSMT_Artifact
The artifact for SecSMT paper -- Usenix Security 2022
H-Y-B/sifive-blocks
Common RTL blocks used in SiFive's projects
H-Y-B/SPEC-config
SPEC compile
H-Y-B/spectre-attack
Example of using revealed "Spectre" exploit (CVE-2017-5753 and CVE-2017-5715)
H-Y-B/sys
H-Y-B/vim-config