/RISC-V-MicroArchitecture-Using-TL-Verilog

This repo contains five stage pipeline from TL-Verilog on Makerchip IDE.

RISC-V-MicroArchitecture-Using-TL-Verilog

This repo contains five stage pipeline from TL-Verilog on Makerchip IDE.

PC COUNTER

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FETCH

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DECODE

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INSTRUCTION IMMEDIATE DECODE

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INSTRUCTION DECODE

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REGISTER FILE

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ALU_RW_BRANCHES

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