Pinned Repositories
.vim
vimrc
bao-hypervisor
Bao, a Lightweight Static Partitioning Hypervisor
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
FreeRTOS-RISCV
A port of FreeRTOS for the RISC-V ISA
OpenWrt_x86-r2s-r4s-r5s-N1
Automatic unattended weekly builds of the current OpenWrt development master branch for X86/64, NanoPi R2S, NanoPi R4S, NanoPi R2C, Phicomm N1, NanoPi NEO3, 树莓派 4B, DoorNet1, DoorNet2, 香橙派 Orange Pi R1 Plus, 香橙派 Orange Pi R1 Plus LTS, 红米AX6, 小米AX3600, 小米AX9000, 红米AX6S/小米AX3200, 红米AC2100, 小米AC2100, 小米CR6606/TR606(联通版), CR6608/TR608(移动版), CR6609/TR609(电信版), 小米4, 小米 R3G, 小米 R3P, 小娱C5, newifi-d2, H1 Box, 贝壳云 P1 , 我家云 lL Pro, x96 Max, 微加云 V-Plus, 章鱼星球 ZYXQ, GT-King, Odroid N2, MXQ Pro+
picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
riscv-dv
Random instruction generator for RISC-V processor verification
riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
Riscy-SoC
Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
shared-lede
定制编译OpenWrt固件
HaibaraMegumi's Repositories
HaibaraMegumi/.vim
vimrc
HaibaraMegumi/bao-hypervisor
Bao, a Lightweight Static Partitioning Hypervisor
HaibaraMegumi/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
HaibaraMegumi/FreeRTOS-RISCV
A port of FreeRTOS for the RISC-V ISA
HaibaraMegumi/OpenWrt_x86-r2s-r4s-r5s-N1
Automatic unattended weekly builds of the current OpenWrt development master branch for X86/64, NanoPi R2S, NanoPi R4S, NanoPi R2C, Phicomm N1, NanoPi NEO3, 树莓派 4B, DoorNet1, DoorNet2, 香橙派 Orange Pi R1 Plus, 香橙派 Orange Pi R1 Plus LTS, 红米AX6, 小米AX3600, 小米AX9000, 红米AX6S/小米AX3200, 红米AC2100, 小米AC2100, 小米CR6606/TR606(联通版), CR6608/TR608(移动版), CR6609/TR609(电信版), 小米4, 小米 R3G, 小米 R3P, 小娱C5, newifi-d2, H1 Box, 贝壳云 P1 , 我家云 lL Pro, x96 Max, 微加云 V-Plus, 章鱼星球 ZYXQ, GT-King, Odroid N2, MXQ Pro+
HaibaraMegumi/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
HaibaraMegumi/riscv-dv
Random instruction generator for RISC-V processor verification
HaibaraMegumi/riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
HaibaraMegumi/Riscy-SoC
Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
HaibaraMegumi/shared-lede
定制编译OpenWrt固件
HaibaraMegumi/tinyriscv
A very simple and easy to understand RISC-V core.