HanJinChi

undergraduate:ShanDong University(2018-2022) postgraduate:Institute of Information Engineering(2022-2025)

Pinned Repositories

cache-model
A behavioural cache model for analysing the cache behaviour under side-channel attack.
Language:C++22 2 03
FlexiCAS
A Flexible Cache Architectural Simulator
Language:C++6 1 133
cache-model
A behavioural cache model for analysing the cache behaviour under side-channel attack.
Language:C++00
nvboard
NJU Virtual Board
Language:C++00
prism
Modular, flexible, cross-platform workload profiling and characterization
Language:C00
ysyx-workbench
Language:C00
RISC-V-book
A translation project of the RISC-V reader
175 11 2042

HanJinChi's Repositories

HanJinChi/cache-model
A behavioural cache model for analysing the cache behaviour under side-channel attack.
Language:C++00
HanJinChi/nvboard
NJU Virtual Board
Language:C++00
HanJinChi/prism
Modular, flexible, cross-platform workload profiling and characterization
Language:C00
HanJinChi/ysyx-workbench
Language:C00