HaogeL

Pinned Repositories

apb_uart_UVM_structure
Language:SystemVerilog40
chisel-book
Digital Design with Chisel
Language:TeX0 0 00
chisel-lab
Lab exercises for Chisel in the digital electronics 2 course at DTU
Language:Scala0 0 00
CommunicationOnOpenCV
This repo provides basic communication functions based on OpenCV framework.
Language:Jupyter Notebook00
DAFIP
Digital ASIC FPGA IP examples
Language:C++00
MIPSCPU
Classic CPU pipeline implementation. ISA: MIPS32Rel1
Language:SystemVerilog00
multiplication_based_divider
Language:SystemVerilog0 2 00
MyRocketchip
an affable rocketchip
Language:Verilog00
symbol_timing_sync
Symbol Timing Synchronization Simulation
Language:MATLAB54 5 212

HaogeL's Repositories

HaogeL/apb_uart_UVM_structure
Language:SystemVerilog40
HaogeL/chisel-book
Digital Design with Chisel
Language:TeX0 0 00
HaogeL/chisel-lab
Lab exercises for Chisel in the digital electronics 2 course at DTU
Language:Scala0 0 00
HaogeL/CommunicationOnOpenCV
This repo provides basic communication functions based on OpenCV framework.
Language:Jupyter Notebook00
HaogeL/DAFIP
Digital ASIC FPGA IP examples
Language:C++00
HaogeL/MIPSCPU
Classic CPU pipeline implementation. ISA: MIPS32Rel1
Language:SystemVerilog00
HaogeL/multiplication_based_divider
Language:SystemVerilog0 2 00
HaogeL/MyRocketchip
an affable rocketchip
Language:Verilog00