HarukaPoi

FRT-Detection

Fruit image classification

Haruka

PANet

Code for our ICCV 2019 paper PANet: Few-Shot Image Semantic Segmentation with Prototype Alignment

ridecore

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

RISCV-RV32I

Hardware implementation of RV32IM

ScreenShare

tcp聊天+文件传输，udp屏幕共享

USTCRVSoC

一个用 SystemVerilog 编写的，基于 RISC-V 的 SoC

HarukaPoi/FRT-Detection

Fruit image classification

HarukaPoi/Haruka

HarukaPoi/PANet

Code for our ICCV 2019 paper PANet: Few-Shot Image Semantic Segmentation with Prototype Alignment

HarukaPoi/ridecore

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

HarukaPoi/RISCV-RV32I

Hardware implementation of RV32IM

HarukaPoi/ScreenShare

tcp聊天+文件传输，udp屏幕共享

HarukaPoi/USTCRVSoC

一个用 SystemVerilog 编写的，基于 RISC-V 的 SoC