Hasan0712
Computer System Engineering (Student) | Research Trainee At MERL | RISC V | VHDL
Micro Electronics Research Lab (MERL)Karachi,Sindh,Pakistan.
Pinned Repositories
FPGA-TANG-NANO-9K
This repo contains practice of basic codes of logic gates and using input through buttons
OpenLane_verification
RTL-Practice
rv32i-sv
This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog
Single-Cycle-Risc-V-32I
This repo contains Single cycle Risc V 32I processor on verilog.
Verilog-Practice
Basic circuits on verilog
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
rv32i-sv
This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog
Hasan0712's Repositories
Hasan0712/FPGA-TANG-NANO-9K
This repo contains practice of basic codes of logic gates and using input through buttons
Hasan0712/rv32i-sv
This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog
Hasan0712/OpenLane_verification
Hasan0712/RTL-Practice
Hasan0712/Verilog-Practice
Basic circuits on verilog
Hasan0712/Single-Cycle-Risc-V-32I
This repo contains Single cycle Risc V 32I processor on verilog.