Implementation of MIPS Single Cycle (using SystemVerilog)
Instructions allowed :-
| Instructio | Type | OPCODE |
|---|---|---|
| LW | I | 100011 |
| SW | I | 101011 |
| BEQ | I | 000100 |
| BNE | I | 000101 |
| ADDI | I | 001000 |
| ORI | I | 001101 |
| ADD | R | 000000 |
| SUB | R | 000000 |
| AND | R | 000000 |
| OR | R | 000000 |
| SLT | R | 000000 |
| J | J | 000010 |
Project is done =))