/FPGA-16-bit-PRNG

seeded 16-bit PRNG FPGA

Primary LanguageMathematica

Quantus Software required

8-Bit Right Shift Register which handled the pipelining of the seed into the Randomizer state machine.

For the 8-Bit RSR there are eight D-Flip flip flops with equivalent number of multiplexers to create a right shift cascading register.

Then the 16-bit data is decoded such that the numbers can be displayed by the 4-bit 7 segment display