Pinned Repositories
MIPS-1
MIPS core designed in only 6 days
566_project
Source repository for 566 class project
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
adeb
A debian-based shell environment designed for Android and adb
aes
amiga2000-gfxcard
MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog
anbox
Anbox is a container-based approach to boot a full Android system on a regular GNU/Linux system
android
CarbonROM Manifest
Android-ChatHead
Floating ChatHead for Android app, like FB messenger.
android-command-line
Bunch of helper scripts to use Android from command line
IngenicC's Repositories
IngenicC/Infinite-ISP
A camera ISP (image signal processor) pipeline that contains modules with simple to complex algorithms implemented at the application level.
IngenicC/awesome-chatgpt-prompts
This repo includes ChatGPT prompt curation to use ChatGPT better.
IngenicC/ghidra
Ghidra is a software reverse engineering (SRE) framework
IngenicC/hal
HAL – The Hardware Analyzer
IngenicC/sliver
Adversary Emulation Framework
IngenicC/Ingenic
Official dahliaOS website
IngenicC/FPGADesignElements
A self-contained online book containing a library of FPGA design modules and related coding/design guides.
IngenicC/linux-insides
A little bit about a linux kernel
IngenicC/litex
Build your hardware, easily!
IngenicC/gem5
This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.
IngenicC/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
IngenicC/rocket-chip
Rocket Chip Generator
IngenicC/IngenicC.github.io
BOOM Website: News, Docs, and more!
IngenicC/IDBs
Analyses in IDA/Hex-Rays
IngenicC/espresso-logic-minimizer
A Node.js bridge to the Espresso heuristic logic minimizer original C code
IngenicC/ece5745-S01-front-end
Section 01: ASIC Flow Front-End
IngenicC/ipcores
A collection of IP's in verilog and chisel for ASIC/FPGA applications
IngenicC/opentitan
OpenTitan: Open source silicon root of trust
IngenicC/OpenRAM
An open-source static random access memory (SRAM) compiler.
IngenicC/DREAMPlace
Deep learning toolkit-enabled VLSI placement
IngenicC/netgen
Netgen complete LVS tool for comparing SPICE or verilog netlists
IngenicC/OpenFPGA
An Open-source FPGA IP Generator
IngenicC/OpenLane
This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
IngenicC/caravel_user_project
https://caravel-user-project.readthedocs.io
IngenicC/caravel_user_project_analog
IngenicC/skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
IngenicC/FABulous
Fabric generator and CAD tools
IngenicC/ebpf-for-windows
eBPF implementation that runs on top of Windows
IngenicC/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
IngenicC/verilog-ethernet
Verilog Ethernet components for FPGA implementation