Irisaka

Irisaka's Stars

• Atmosphere-NX/Atmosphere

  Atmosphère is a work-in-progress customized firmware for the Nintendo Switch.

  Language:C++15.3k1.3k

• XUANTIE-RV/openc906

  OpenXuantie - OpenC906 Core

  Language:Verilog328103

• XUANTIE-RV/openc910

  OpenXuantie - OpenC910 Core

  Language:Verilog1.2k314

• bpc-clone/bpc_chrome_support

  5.2k398

• Sak32009/GetDataFromSteam-SteamDB

  953209

• pointfeev/CreamInstaller

  Automatically finds all installed Steam, Epic and Ubisoft games with their respective DLC-related DLL locations on the user's computer, parses SteamCMD, Steam Store and Epic Games Store for user-selected games' DLCs, then provides a very simple graphical interface utilizing the gathered information for the maintenance of DLC unlockers.

  Language:C#3.9k

• chatanywhere/GPT_API_free

  Free ChatGPT API Key，免费ChatGPT API，支持GPT4 API（免费），ChatGPT国内可用免费转发API，直连无需代理。可以搭配ChatBox等软件/插件使用，极大降低接口使用成本。国内即可无限制畅快聊天。

  Language:Python26.2k1.9k

• yt-dlp/yt-dlp

  A feature-rich command-line audio/video downloader

  Language:Python94.5k7.4k

• bloc97/Anime4K

  A High-Quality Real Time Upscaler for Anime Video

  Language:Jupyter Notebook18.6k1.4k

• AIsouler/GKD_subscription

  GKD 第三方订阅规则

  Language:TypeScript4.1k144

• gkd-kit/gkd

  基于无障碍，高级选择器，订阅规则的自定义屏幕点击 Android 应用 | An Android APP with custom screen tapping based on Accessibility, Advanced Selectors, and Subscription Rules

  Language:Kotlin23.4k1.2k

• USTC-System-Courses/CECS-Lab

  Language:C3111

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.3k705

• eugene-tarassov/vivado-risc-v

  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

  Language:Tcl877197

• torvalds/linux

  Linux kernel source tree

  Language:C185k54.5k

• ultraembedded/riscv

  RISC-V CPU Core (RV32IM)

  Language:Verilog1.3k238

• adam-maj/tiny-gpu

  A minimal GPU design in Verilog to learn how GPUs work from the ground up

  Language:SystemVerilog7.2k547

• ultraembedded/cores

  Various HDL (Verilog) IP Cores

  Language:Verilog717215

• Delppine1024/TGreen

  Some files work well on T v1.1 (The latest support v1.8.10/1.8.3-dev), Powered by TC

  58622

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.4k710

• ACL4SSR/ACL4SSR

  SSR 去广告ACL规则/SS完整GFWList规则/Clash规则碎片，Telegram频道订阅地址

  4k1.4k

• Mythologyli/zju-connect

  ZJU RVPN 客户端的 Go 语言实现

  Language:Go36125

• SubConv/ZJU-Rule

  Language:Python7521

• lengmo23/ZJURule

  Backup for ZJU-Rule. Thanks for Mythli.

  27

• analogdevicesinc/hdl

  HDL libraries and projects

  Language:Verilog1.6k1.5k

• open-sdr/openwifi-hw

  open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

  Language:Verilog712242

• bilibili/ailab

  Language:Python5.7k551

• Oregon-7/PC_Building_Guide

  24

• jellyfin/jellyfin

  The Free Software Media System - Server Backend & API

  Language:C#36k3.3k

• vernesong/OpenClash

  A Clash Client For OpenWrt

  Language:JavaScript18.1k3.3k