This 5-stage pipelined processor, built with Harvard architecture, enhances performance through parallelism and simultaneous access to separate instruction and data memory. It employs full forwarding to minimize data hazards and dynamic 1-bit branch prediction to optimize control flow. The processor efficiently handles interrupts and exceptions, ensuring robust operation. A custom assembler is included to translate high-level mnemonic instructions into machine code tailored to the processor's instruction set, maximizing the processor's capabilities.
Here is the schematic diagram of our processor:
https://drive.google.com/file/d/1XO8V1skts5mGuL41N_zzHYwbW1lZ3_6u/view?usp=sharing
You can find more about the project specifics in the project document and final report.