This repository contains arithmetic functions in systemverilog for use in hardware(FPGAs, ASIC, VLSI) development
The logic behind the algorithms is based off research papers and textbooks (cited in detail in README.md for the specific alogrithm
This project is at it's early stages and formal verification has not yet been implemented
Use of these functions is at your own risk
Addition algorithms included are:
32-bit Carry Skip Adder Carry Select(Bedrij) Carry look ahead
Interpolated Look Up Table Division Newton Raphson Division Goldschdmit Division
Note: The original idea for this repository is based off a previous internship that had me create certain arithmetic functions. The code created here is entirely new and does not pull from my code created at the former company I interned at.