Pinned Repositories
adpll
awesome-opensource-hardware
List of awesome open source hardware tools, generators, and reusable designs
darknet
Convolutional Neural Networks
iob-axi
iob-cache
Verilog configurable cache
iob-div
Verilog Divider Cores
iob-fir
iob-interconnect
handle bus interconnection
iob-knn
iob-lib
JDLopes's Repositories
JDLopes/pt-float
JDLopes/darknet
Convolutional Neural Networks
JDLopes/iob-soc-sha
SoC to run the program in software with or without acceleration using VERSAT2.0
JDLopes/awesome-opensource-hardware
List of awesome open source hardware tools, generators, and reusable designs
JDLopes/iob-lib
JDLopes/iob-div
Verilog Divider Cores
JDLopes/iob-versat
Coarse Grained Reconfigurable Array
JDLopes/iob-soc
RISC-V System on Chip Template Based on the picorv32 Processor
JDLopes/iob-plic
JDLopes/iob-cache
Verilog configurable cache
JDLopes/iob-uart
JDLopes/report_template
JDLopes/iob-picorv32
IOb_SoC version of the Picorv32 RISC-V Verilog IP core
JDLopes/iob-soc-wsn-em
JDLopes/iob-soc-vexriscv
JDLopes/iob-mem
Verilog behavioral description of various memories
JDLopes/iob-vexriscv
JDLopes/iob-axi
JDLopes/verilog-axi
Verilog AXI components for FPGA implementation
JDLopes/iob-tex
JDLopes/iob-interconnect
handle bus interconnection
JDLopes/adpll
JDLopes/iob-timer
Simple Timer IP Core in Verilog
JDLopes/iob-soc-knn
JDLopes/iob-knn
JDLopes/iob-fir
JDLopes/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
JDLopes/iob-mul