JakobRat

Electronic Engineering Student @ Johannes Kepler University

Linz, Austria

Pinned Repositories

kvic_336007_ws22
Course material for 336.007 (Prof. Pretl) in WS22 at JKU
Language:Verilog2 1 00
tt05-analog-test
Analog test macro (500kHz ring oscillator, 3-bit DAC) for TinyTapeout 05.
Language:Tcl4 2 12
caravel_user_project
https://caravel-user-project.readthedocs.io
Language:Verilog0 0 00
OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
Language:Verilog0 0 00
RALF
Reinforcement learning assisted analog layout design flow.
Language:Python18 4 37

JakobRat's Repositories

JakobRat/RALF
Reinforcement learning assisted analog layout design flow.
Language:Python18 4 37
JakobRat/caravel_user_project
https://caravel-user-project.readthedocs.io
Language:Verilog0 0 00
JakobRat/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
Language:Verilog0 0 00