Lab 2: Four-bit Two's Complement Adder/Subtractor
C3C Jasper Arneberg
M6A ECE 281
Dr. Neebel
| A | B | Cin | Sum | Cout |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
Sum = AB'C' + A'BC' + A'B'C + ABC Cout = AC + BC + AB
The schematic for the full adder was drawn in dot notation for a programmable logic array with an OR array and an AND array.
| A | B | Cin | Sum | Cout |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
The truth table of expected results and the truth table derived from the simulation waveform match exactly. This demonstrates that the full adder VHDL code works as it should.
Here is the final circuit schematic. The design uses four full adder components, labeled 3 through 0 as can be seen. The final design also implements the logic from four different multiplexers. These multiplexers switch the input to the adder between B and B' based on whether or not the subtraction button is enabled.
The four-bit adder/subtractor waveform can be seen below. There are 512 potential combinations, each one corresponding to 1ns. Below the waveform is the console output. Notice that it states "Test completed successfully."
Throughout this lab, it was necessary to constantly break each problem down into smaller pieces. The first task was to make the full adder work. After that, the four-bit adder had to function correctly before moving on. The overflow was pretty easy to implement with a single line of code. The subtractor, on the other hand, took quite a bit of work, because it required multiplexer behavior.
Creating the testbench proved to be a challenge. This was the first exercise or lab that required for loops to test. Since the syntax of VHDL can be very foreign, I had to research how to do for loops. I also looked up how to print error messages stating why certain numbers were not adding up correctly.
I demonstrated basic functionality of four-bit adder to Dr. Neebel at 1424 on 10 Feb 14.
I demonstrated complete funtionality including subtraction and overflow detection to Dr. Neebel at 1322 on 12 Feb 14.
C3C El-Saawy helped me with determining the initial setup of the four-bit adder/subtractor. He also told me to change the reporting severity to FAILURE in the testbench to stop the test if there's an assertion error.
I learned how to use for loops in a testbench and report results:
http://www.seas.upenn.edu/~ese171/vhdl/VHDLTestbench.pdf
I used this site to understand why the overflow is Cout(2) xor Cout(3):
http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Comb/overflow.html