Pinned Repositories
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
AutoSA
AutoSA: Polyhedral-Based Systolic Array Compiler
bcc
BCC - Tools for BPF-based Linux IO analysis, networking, monitoring, and more
Calculate-X-Factorial-in-Assemble-Language-LC3-
note: LC3 ISA
calico
Cloud native networking and network security
cilium
corundum
Open source FPGA-based NIC and platform for in-network compute
DeepMatch
DeepMatch: Practical Deep Packet Inspection in the Data Plane using Network Processors
distributed-pytorch
Distributed, mixed-precision training with PyTorch
dotfiles
JeffMY05's Repositories
JeffMY05/AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
JeffMY05/AutoSA
AutoSA: Polyhedral-Based Systolic Array Compiler
JeffMY05/bcc
BCC - Tools for BPF-based Linux IO analysis, networking, monitoring, and more
JeffMY05/calico
Cloud native networking and network security
JeffMY05/cilium
JeffMY05/corundum
Open source FPGA-based NIC and platform for in-network compute
JeffMY05/DeepMatch
DeepMatch: Practical Deep Packet Inspection in the Data Plane using Network Processors
JeffMY05/distributed-pytorch
Distributed, mixed-precision training with PyTorch
JeffMY05/dotfiles
JeffMY05/elastica
Software to simulate the dynamics of filaments that, at every cross-section, can undergo all six possible modes of deformation, allowing the filament to bend, twist, stretch and shear, while interacting with complex environments via muscular activity, surface contact, friction and hydrodynamics.
JeffMY05/flannel
flannel is a network fabric for containers, designed for Kubernetes
JeffMY05/hl5
A 32-bit RISC-V Processor Designed with High-Level Synthesis
JeffMY05/HLS-Tiny-Tutorials
JeffMY05/hls4ml
Machine learning in FPGAs using HLS
JeffMY05/HLS_BLSTM
The community version of HLS_BLSTM (A BLSTM FPGA accelerator of an OCR appilcation, using CAPI/SNAP))
JeffMY05/hlslib
A collection of extensions for Vivado HLS and Intel FPGA OpenCL to improve developer quality of life.
JeffMY05/hyperscan
High-performance regular expression matching library
JeffMY05/kcp
kcp is a prototype of a multi-tenant Kubernetes control plane for workloads on many clusters
JeffMY05/Limago
Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
JeffMY05/pigasus
100Gbps Intrusion Detection and Prevention System
JeffMY05/PytorchToCaffe
Pytorch model to caffe model, supported pytorch 0.3, 0.3.1, 0.4, 0.4.1 ,1.0 , 1.0.1 , 1.2 ,1.3 .notice that only pytorch 1.1 have some bugs
JeffMY05/SkyNet
JeffMY05/tapa
JeffMY05/ThymesisFlow
Memory Disaggregation on POWER9 with OpenCAPI
JeffMY05/uiucthemes
RMarkdown Templates for UIUC Theme-Oriented Documents
JeffMY05/Understanding-network-stack-overheads-SIGCOMM-2021
Tools for profiling the Linux network stack.
JeffMY05/UniNet
JeffMY05/Vitis_with_100Gbps_TCP-IP
100 Gbps TCP/IP stack for Vitis shells
JeffMY05/Vivado-HLS-Report-Parser
A parser to export the contents of HLS Vivado synthesis reports to a CSV file
JeffMY05/xup_vitis_network_example
VNx: Vitis Network Examples