Jiahua-Gong

Jiahua-Gong's Stars

• syntacore/scr1

  SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  Language:SystemVerilog854275

• chipsalliance/Cores-VeeR-EH1

  VeeR EH1 core

  Language:SystemVerilog817221

• veripool/verilog-mode

  Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

  Language:SystemVerilog25990

• mark-marinas/pe_tools-vcdToPattern

  tool for converting vcd(value change dump) to ate pattern.

  Language:C112

• andri27-ts/Reinforcement-Learning

  Learn Deep Reinforcement Learning in 60 days! Lectures & Code in Python. Reinforcement Learning + Deep Learning

  Language:Jupyter Notebook4.2k622

• SpinalHDL/SpinalHDL

  Scala based HDL

  Language:Scala1.6k322

• The-OpenROAD-Project/OpenLane

  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  Language:Python1.3k372

• seabeam/yuu_ahb

  UVM AHB VIP

  Language:SystemVerilog7518

• ZcashFoundation/zcash-fpga

  Zcash FPGA acceleration engine

  Language:SystemVerilog11946