JiawenDeng

JiawenDeng's Stars

• datawhalechina/awesome-compression

  模型压缩的小白入门教程

  21329

• JansonYuan/Pytorch-Camp

  Language:Python368228

• greebear/pytorch-learning

  Language:Jupyter Notebook190107

• lxysl/mit-bih_ecg_recognition

  MIT-BIH ECG recognition using 1d CNN with TensorFlow2 and PyTorch

  Language:HTML14030

• openhwgroup/cv32e40p

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  Language:SystemVerilog975426

• cxdzyq1110/NPU_on_FPGA

  在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。

  Language:Verilog20542

• vortexgpgpu/vortex

  Language:Verilog1.3k273

• ym31433/NPU-Architecture

  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations

  Language:Verilog185

• arc-research-lab/CHARM

  CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture

  Language:C++12421

• hypocrasy/NPUSoC

  第四届全国大学生嵌入式比赛SoC

  Language:Verilog72

• thousrm/universal_NPU-CNN_accelerator

  hardware design of universal NPU(CNN accelerator) for various convolution neural network

  Language:Verilog807

• dineshannayya/riscduino

  Arduino compatible Risc-V Based SOC

  Language:Tcl13923

• basicmi/AI-Chip

  A list of ICs and IPs for AI, Machine Learning and Deep Learning.

  Language:PHP1.6k274

• ahmedshahein/DSP-RTL-Lib

  RTL Verilog library for various DSP modules

  Language:Verilog8331

• hunterlew/convolution_network_on_FPGA

  CNN acceleration on virtex-7 FPGA with verilog HDL

  Language:Verilog407128

• sudhamshu091/32-Verilog-Mini-Projects

  Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

  Language:Verilog598116

• cxdzyq1110/posture_recognition_CNN

  To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different responses to all kinds of human's postures. But the process is very difficult as well, because usually it is very slow and power-consuming, and requires a very large memory space. Here we focus on real-time posture recognition, and try to make the machine "know" what posture we make. The posture recognition system is consisted of DE10-Nano SoC FPGA Kit, a camera, and an HDMI monitor. SoC FPGA captures video streams from the camera, recognizes human postures with a CNN model, and finally shows the original video and classification result (standing, walking, waving, etc.) via HDMI interface.

  Language:Verilog5117

• AlexKly/Simple-Voice-Activity-Detector-using-MFCC-based-on-FPGA-Kintex

  Voice Activity Detector based on MFCC features and DNN model

  Language:VHDL143

• lp6m/ImageDetectionHW2

  HOG + SVM on FPGA

  Language:C++2512

• HermannLiang/msc-stress

  MSc Project: Quantifying Stress Pattern. A 9-month individual research project, as a part of my MSc Communication & Signal Processing at Imperial College London. (ECG, HRV, SVM, LSTM, MATLAB)

  Language:MATLAB175

• venturit/ecg_classification

  Code for training and test machine learning classifiers on MIT-BIH Arrhyhtmia database

  Language:Matlab1

• mondejar/ecg-classification

  Code for training and test machine learning classifiers on MIT-BIH Arrhyhtmia database

  Language:Python535194

• AshwinSundar/Empirical-Mode-Decomposition-for-MIT-BIH-Arrhythmia-Data

  Biomedical Engineering Master's Project at Arizona State University

  Language:Matlab3

• arshanh/CNN-arrhythmia-dection

  A 1D Convolutional Neural Network I trained to detect 5 types of arrhythmia in heartbeats taken from the MIT/BIH Arrhythmia Database

  Language:Matlab137

• fengyulin1996/Verilog-DSP

  FIR，FFT based on Verilog

  Language:Verilog13

• danieleninni/fir-filter-fpga

  Design and implementation of a reconfigurable FIR filter in FPGA

  Language:VHDL112

• mabrains/PLL_design

  PLL Designs on Skywater 130nm MPW

  Language:Verilog20

• loykylewong/FPGA-Application-Development-and-Simulation

  《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

  Language:SystemVerilog12629

• uwemeyerbaese/DSP_with_FPGAs_ed4

  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3

  Language:Verilog4212

• damdoy/ice40_ultraplus_examples

  Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

  Language:Verilog25446