Pinned Repositories
256-Point_Parallel_FFT_DIF
32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
acoular
Library for acoustic beamforming
Aegean
The Aegean source finding program and associated tools
aimfast
An Astronomical Image Fidelity Assessment Tool
cocotb
Coroutine Co-simulation Test Bench
CorrelX
CorrelX: A Cloud-Based Software Correlator for Very Long Baseline Interferometry (VLBI)
dblclockfft
A configurable C++ generator of pipelined Verilog FFT cores
DDS
A DDS core written in VHDL.
Polyphase-FIR-Channelized-Receiver
16 channel receiver and transmitter using Polyphase FIR filters.
JiyunLi-shao's Repositories
JiyunLi-shao/Polyphase-FIR-Channelized-Receiver
16 channel receiver and transmitter using Polyphase FIR filters.
JiyunLi-shao/32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
JiyunLi-shao/Aegean
The Aegean source finding program and associated tools
JiyunLi-shao/aimfast
An Astronomical Image Fidelity Assessment Tool
JiyunLi-shao/cocotb
Coroutine Co-simulation Test Bench
JiyunLi-shao/dblclockfft
A configurable C++ generator of pipelined Verilog FFT cores
JiyunLi-shao/DDS
A DDS core written in VHDL.
JiyunLi-shao/FFT-FPGA
Repository for implementation of Radix-2 algorithm. This project is developed in VHDL code.
JiyunLi-shao/fp23fftk
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
JiyunLi-shao/fpbinary
Binary fixed point library for Python.
JiyunLi-shao/fpga_snark_prover
An acceleration engine for proving SNARKS over the bn128 curve, targeted for AWS FPGAs
JiyunLi-shao/Guide-to-FPGA-Implementation-of-Arithmetic-Functions
Examples from the book by Deschamps et al. https://www.amazon.com/Implementation-Arithmetic-Functions-Electrical-Engineering/dp/9400729863
JiyunLi-shao/intfftk
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
JiyunLi-shao/linux
Linux kernel source tree
JiyunLi-shao/marlin
A Rust library for the Marlin preprocessing zkSNARK
JiyunLi-shao/mkat_fpga_tests
A Correlator-beamforming unit-testing based framework for MeerKAT signal processing.
JiyunLi-shao/modexp
Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
JiyunLi-shao/Modexpowering3
a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier
JiyunLi-shao/modular-nested-exponentiation
An algorithm that computes modular nested exponentiation efficiently.
JiyunLi-shao/Modular_exponentiation_in_VHDL
Modular exponentiation in VHDL with Montgomery's multiplication enhanced with Karatsuba's algorithm.
JiyunLi-shao/Parallel_CCSDS-123.0-B-1
An implementation of the CCSDS 123.0-B-1 standard for FPGA with parallel capabilities.
JiyunLi-shao/pfb_introduction
An interactive introduction to the polyphase filterbank technique for radio astronomy spectrometers
JiyunLi-shao/PFBSIM
My attempt at making a polyphase filter bank (PFB) simulator as part of my final year project for an undergraduate physics degree
JiyunLi-shao/pyfda
Python Filter Design Analysis Tool
JiyunLi-shao/PYNQ
Python Productivity for ZYNQ
JiyunLi-shao/requant_utils
Convert 8-bit data to 2-bit data in python
JiyunLi-shao/snarkVM
A Virtual Machine for Zero-Knowledge Executions
JiyunLi-shao/vcstools
A suite of tools for processing MWA-VCS data
JiyunLi-shao/vdf-fpga
A low latency modulo squaring algorithm using Montgomery multiplication, submitted to the VDF FPGA design competition, targeting AWS FPGAs. Was awarded first prize for lowest latency in alternative approaches category.
JiyunLi-shao/zcash-fpga
Zcash FPGA acceleration engine