Jjateen/7T-SRAM-MCPL

This project showcases the design and simulation of a 7T MCPL SRAM using adiabatic logic for low-power efficiency, developed for ECL 312 at IIIT Nagpur. It compares the 6T and 7T SRAM designs in terms of power, energy, and stability, with simulations done in WinSpice and Microwind.

SystemVerilog