Pinned Repositories
compas-ft-riscv
repo to house various LLVM based SIHFT passes for RISCV 32/64 soft error resilience
etiss
Extendable Translating Instruction Set Simulator
FreeRTOS-Emulator
POSIX based FreeRTOS emulator with SDL2 graphics interface and multiple async communications interfaces, aiming to make it possible to teach FreeRTOS without embedded hardware using similar processes
softvector
Vector arithmetic library targeting simulation of Vector Processing Units (VPUs) for various targets, e.g., ETISS.
SystemC-Components
A SystemC productivity library for virtual platform development utilizing SCV and TLM2.0
VPV-Peripherals
Library of example SystemC/TLM peripherals for various SoCs based on the SCS library
SystemC-Components
A SystemC productivity library: https://minres.github.io/SystemC-Components/
etiss
Extendable Translating Instruction Set Simulator
etiss-sc
SystemC/TLM2.0 productivity library wrapping the Extendable Instruction Set Simulator ETISS as a tlm cpu core.
vrtlmod
vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/Clang-Tools and generates a fault injection API.
JoGei's Repositories
JoGei/compas-ft-riscv
repo to house various LLVM based SIHFT passes for RISCV 32/64 soft error resilience
JoGei/etiss
Extendable Translating Instruction Set Simulator
JoGei/FreeRTOS-Emulator
POSIX based FreeRTOS emulator with SDL2 graphics interface and multiple async communications interfaces, aiming to make it possible to teach FreeRTOS without embedded hardware using similar processes
JoGei/softvector
Vector arithmetic library targeting simulation of Vector Processing Units (VPUs) for various targets, e.g., ETISS.
JoGei/SystemC-Components
A SystemC productivity library for virtual platform development utilizing SCV and TLM2.0
JoGei/VPV-Peripherals
Library of example SystemC/TLM peripherals for various SoCs based on the SCS library