This is a basic single cycle risc-v RV32I implementation meant for learning purposes. Programmed in verilog and simulated in modelsim.
addi x1, x0, 1
addi x2, x0, 2
add x3, x1, x2
sw x3, 0(x0)
addi x3, x3, -1
bne x3, x0, -4
xor x3, x2, x0
jal x1, -28