Pinned Repositories
CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM).
linker-script-basics
A quick introduction to linker scripts for the GNU linker.
litex
Build your hardware, easily!
litex-boards
LiteX boards files
misc
Random stuff -- small demos/tutorials, etc.
portfolio
pythondata-cpu-vexriscv
Python module containing verilog files for vexriscv cpu (for use with LiteX).
RISC-V_RV32I_Cheat_Sheet
Concise, single page summary of RISC-V RV32I instructions and pseudo-instructions.
step
tour-of-nmigen
A concise overview of the nMigen HDL toolbox.
JosephBushagour's Repositories
JosephBushagour/linker-script-basics
A quick introduction to linker scripts for the GNU linker.
JosephBushagour/tour-of-nmigen
A concise overview of the nMigen HDL toolbox.
JosephBushagour/portfolio
JosephBushagour/RISC-V_RV32I_Cheat_Sheet
Concise, single page summary of RISC-V RV32I instructions and pseudo-instructions.
JosephBushagour/CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM).
JosephBushagour/litex
Build your hardware, easily!
JosephBushagour/litex-boards
LiteX boards files
JosephBushagour/misc
Random stuff -- small demos/tutorials, etc.
JosephBushagour/pythondata-cpu-vexriscv
Python module containing verilog files for vexriscv cpu (for use with LiteX).
JosephBushagour/step