Jouwy

Southern University of Science and Technology

Pinned Repositories

Digital-Piano
Digital Piano: FPGA project in Verilog based on Xilinx Atrix-7 EGO1 - SUSTech's project of course CS207: Digital Logic in Fall 2023 - Score: 120/100
Language:Verilog00
RISC-V-CPU
RISC-V CPU: Single-Cycle Processor for RISC-V ISA Built in Verilog - SUSTech's project of course CS202: Computer Organization in Spring 2024 - Score: 104.5/100
Language:VHDL00
Shenzhen-Metro
Shenzhen Metro: Metro Management System - Database and API Design Projects - SUSTech's projects of course CS307: Principles of Database System in Spring 2024 - Scores: 95/100 for Project 1 and 102/100 for Project 2
Language:Java00
Shenzhen-Metro
Shenzhen Metro: Metro Management System - Database and API Design Projects - SUSTech's projects of course CS307: Principles of Database System in Spring 2024 - Scores: 95/100 for Project 1 and 102/100 for Project 2
Language:Java0 2 01

Jouwy/Digital-Piano
Digital Piano: FPGA project in Verilog based on Xilinx Atrix-7 EGO1 - SUSTech's project of course CS207: Digital Logic in Fall 2023 - Score: 120/100
Language:Verilog00
Jouwy/RISC-V-CPU
RISC-V CPU: Single-Cycle Processor for RISC-V ISA Built in Verilog - SUSTech's project of course CS202: Computer Organization in Spring 2024 - Score: 104.5/100
Language:VHDL00
Jouwy/Shenzhen-Metro
Shenzhen Metro: Metro Management System - Database and API Design Projects - SUSTech's projects of course CS307: Principles of Database System in Spring 2024 - Scores: 95/100 for Project 1 and 102/100 for Project 2
Language:Java00