JoyenBenitto
I'm a developer with a passion to solve complex problems and automate boring tasks.
@incoresemiIndia
Pinned Repositories
CUDA-101-Workshop
CUDA-101 Workshop
Antenna_generator
Antenna_generator is a tool developed with researchers in the field of antenna design in mind. In a nutshell antenna_generator is a python package that allows you to generate microstrip patch antenna in the HFSS software, we have added support for optimizations like cut-out, slots and L slot.
Bluespec_noob
Learning bluespec with bunch of tutorials and example codes
CUDA-101-Workshop
CUDA-101 Workshop
cuda_workshop
Understanding data level parallelism with CUDA
fleetvision
FleetVision - HashCode 11 Hackathon Project
giggle
Giggle is a tiny static site generator
grape
grape is a single cycle RISC-V [RV32I] processor synthesised using SystemVerilog. This project was done as a part of the RISC-V Architecture course(UE20EC302). This my first attempt in building a processor.
physical-design-exploration
In this repo I explore opensource EDA tools and PD of ASIC design flow.
Quark
Quark is a single cycle RV32I RISC-V core, The RTL is written in BlueSpec System Verilog (BSV)
JoyenBenitto's Repositories
JoyenBenitto/Antenna_generator
Antenna_generator is a tool developed with researchers in the field of antenna design in mind. In a nutshell antenna_generator is a python package that allows you to generate microstrip patch antenna in the HFSS software, we have added support for optimizations like cut-out, slots and L slot.
JoyenBenitto/grape
grape is a single cycle RISC-V [RV32I] processor synthesised using SystemVerilog. This project was done as a part of the RISC-V Architecture course(UE20EC302). This my first attempt in building a processor.
JoyenBenitto/Quark
Quark is a single cycle RV32I RISC-V core, The RTL is written in BlueSpec System Verilog (BSV)
JoyenBenitto/giggle
Giggle is a tiny static site generator
JoyenBenitto/fleetvision
FleetVision - HashCode 11 Hackathon Project
JoyenBenitto/physical-design-exploration
In this repo I explore opensource EDA tools and PD of ASIC design flow.
JoyenBenitto/Bluespec_noob
Learning bluespec with bunch of tutorials and example codes
JoyenBenitto/CUDA-101-Workshop
CUDA-101 Workshop
JoyenBenitto/cuda_workshop
Understanding data level parallelism with CUDA
JoyenBenitto/go_learn
Learning go
JoyenBenitto/JoyenBenitto
JoyenBenitto/Keleidoscope
Learning LLVM by building a compiler
JoyenBenitto/pes_asic_class
In this repository we begin our journey with simulating basic C code for a RISC-V processor.
JoyenBenitto/riscv-config
RISC-V Configuration Validator