KKIDOL

KKIDOL's Stars

• sqzw-x/mdcx

  Movie metadata scraper

  Language:Python2k266

• bunny965/yolov5-fpga-hardware-acceleration

  网络训练、图像预处理以及部分hend功能是基于pc端实现的，只有主干网络部署在fpga上，片上资源无法支持整个网络所需资源，建议添加外部存储及DDR

  Language:Verilog7111

• ptoupas/amd-open-hardware-23

  This repository provides an FPGA-based solution for executing object detection, focusing specifically on the popular YOLOv5 model architecture.

  Language:Python387

• scy0208/EM-GMM-matlab

  Using EM algorithm for mixed Gaussian distribution clustering

  Language:Matlab2523

• vineeths96/Spectrum-Sensing-for-Cognitive-Radio

  In this repository, we deal with developing an energy detector and a detector based on cyclostationarity for an OFDM based cognitive radio system and implementing and evaluating the performance of these detectors.

  Language:Python3810

• shkrwnd/Deep-Reinforcement-Learning-for-Dynamic-Spectrum-Access

  Using multi-agent Deep Q Learning with LSTM cells (DRQN) to train multiple users in cognitive radio to learn to share scarce resource (channels) equally without communication

  Language:Jupyter Notebook22598

• star2dust/paper-simulation

  Let's reproduce paper simulations of multi-robot systems, formation control, distributed optimization and cooperative manipulation.

  Language:MATLAB34781

• PaulTan94/CSS_DRQN

  Cooperative Spectrum Sensing based on Deep Recurrent Q-Network

  Language:Python163

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.4k716

• google-deepmind/graphcast

  Language:Python5.6k685

• germain-hug/Deep-RL-Keras

  Keras Implementation of popular Deep RL Algorithms (A3C, DDQN, DDPG, Dueling DDQN)

  Language:Python535149

• ufrisk/pcileech

  Direct Memory Access (DMA) Attack Software

  Language:C5.2k760

• dadongshangu/async_FIFO

  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

  Language:SystemVerilog5615

• jessepalomera/10G_EthernetMAC_SystemVerilog_OOP

  Final Project for my course in Advanced Verification with SystemVerilog OOP

  Language:Verilog203

• wbbbbbb123/UVM-based-AHB-bus-SRAM-controller-design-verification-platform-design

  Language:Verilog142

• VerificationExcellence/SystemVerilogReference

  training labs and examples

  Language:SystemVerilog403175

• VerificationExcellence/UVMReference

  Reference examples and short projects using UVM Methodology

  Language:SystemVerilog254154

• taichi-ishitani/tvip-axi

  AMBA AXI VIP

  Language:SystemVerilog367106

• chipsalliance/Cores-VeeR-EH1

  VeeR EH1 core

  Language:SystemVerilog834222

• courageheart/AMBA_APB_SRAM

  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

  Language:SystemVerilog16062

• liangkangnan/tinyriscv

  A very simple and easy to understand RISC-V core.

  Language:C1.1k192

• alexforencich/verilog-axis

  Verilog AXI stream components for FPGA implementation

  Language:Python762232

• alexforencich/verilog-i2c

  Verilog I2C interface for FPGA implementation

  Language:Verilog565175

• freecores/apbi2c

  APB to I2C

  Language:Verilog399

• red435/verilog_APB_SPI_interface

  SPI interface connect to APB BUS with Verilog HDL

  Language:Verilog255

• alexforencich/verilog-pcie

  Verilog PCI express components

  Language:Verilog1.2k310

• DingranFeng/Wireless-Communication-Simulation

  Simulate the real wireless communication environment and compare the modulation performances of BPSK, QPSK, 16QAM, 64QAM.

  Language:MATLAB5917

• visky2096/AHB-to-I2C

  Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C master and I2c slave. The RTL and all the test benches are written in [VERILOG]

  Language:Verilog203

• adki/AMBA_AXI_AHB_APB

  AMBA bus lecture material

  Language:Verilog393130

• GodelMachine/AHB2

  AMBA AHB 2.0 VIP in SystemVerilog UVM

  Language:SystemVerilog14764