KaiLongHu

KaiLongHu's Stars

• 521xueweihan/HelloGitHub

  :octocat: 分享 GitHub 上有趣、入门级的开源项目。Share interesting, entry-level open source projects on GitHub.

  Language:Python97.6k9.8k

• lijin-THU/notes-python3

  中文Python 3笔记

  Language:Jupyter Notebook19154

• opensmartnic/cocotb_primer

  understanding of cocotb （In Chinese Only）

  133

• TerosTechnology/vscode-terosHDL

  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

  Language:VHDL58646

• Digital-EDA/Digital-IDE

  All in one vscode plugin for HDL development

  Language:VHDL44513

• Nitcloud/Digital-IDE

  在vscode上的数字设计开发插件

  Language:Verilog34520

• jackfrued/Python-100-Days

  Python - 100天从新手到大师

  Language:Python160k52.8k

• ljgibbslf/Chinese-Translation-of-PCI-Express-Technology-

  Chinese Translation on <PCI Express Technology Comprehensive Guide to Generations 1.x, 2.x and 3.0> by Mindshare Mindshare

  27896

• cocotb/cocotb

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  Language:Python1.9k530

• AngeloJacobo/UberDDR3

  Opensource DDR3 Controller

  Language:Verilog24638

• xiaochuang-lxc/protocol

  An ASCII Header Generator for Network Protocols

  Language:Python144

• wallento/wavedrompy

  WaveDrom compatible python command line

  Language:Python10024

• xiaochuang-lxc/wavedraw

  draw interface wave by python

  Language:Python151

• fpgasystems/fpga-network-stack

  Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

  Language:C++778275

• corundum/corundum

  Open source FPGA-based NIC and platform for in-network compute

  Language:Verilog1.8k427

• qiujiandong/srio-controller

  在FPGA上实现SRIO收发控制器

  Language:Tcl93

• rakeshgehalot/Ethernet_switch_verification

  Verification of Ethernet Switch System Verilog

  Language:SystemVerilog111

• mcjtag/eth_switch

  Verilog Ethernet Switch (layer 2)

  Language:Verilog3911

• freecores/pid_controller

  PID controller

  Language:Verilog195

• A-suozhang/Verilog_Uart_With_Fifo

  Implemented The UART with FIFO

  Language:Verilog122

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.4k718

• SSHeRun/CS-Xmind-Note

  计算机专业课（408）思维导图和笔记：计算机组成原理（第五版 王爱英），数据结构（王道），计算机网络（第七版 谢希仁），操作系统（第四版 汤小丹）

  9.3k2.1k

• jerrylioon/Solutions-to-HDLbits-Verilog-sets

  Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).

  Language:Verilog8228