Example of how to use yosys, vlog2Verilog and vlog2Spice to generate a RTL verilog file as well as a spice netlist mapped to the sky130 PDK.
You need yosys, which can be build from this repo. To perform the verilog to spice convertion, you need to make the two
binaries vlog2Verilog and vlog2Spice, which can be build from the qflow repo. For all of this to work, you need
these three binaries in your $PATH variable.
The skywater 130nm PDK needs to be install into the /usr/local/share/pdk directory using the open_pdks installation
(check this repo). Otherwise, the scripts won't work.
To synthesize the verilog counter upcounter.v and create a spice netlist aswell just do:
make
If you want to do only the yosys synthesis, you can call:
make synth-yosys
The file synth.spice contains the spice netlist version, mapped to the standard cells of the sky130 PDK.
A bonus feature is to simulate the verilog source code by calling:
make simulate
This will only work on MacOS with GTKwave installed as an app.