/CNN-Accelerator-Implementation-based-on-Eyerissv2

Primary LanguageVerilog

CNN Accelerator Implementation based on Eyerissv2

This is a course project based on Verilog.

A CNN accelerator architecture based on Eyeriss v2 is modeled to progress convolutional layers, full connected layers and depth-conv layers.

RTL

  • GLB_CLUSTER
    • GLB_WGHT
    • GLB_IACT
    • GLB_PSUM

glb.png

  • PE_CLUSTER
  • PE
    • SPad
    • MUX
    • MAC

PE.png

  • ROUTER_CLUSTER

    • ROUTER_IACT
    • ROUTER_WGHT
    • ROUTER_PSUM

image.png

  • HMNOC

    • 4_CLUSTER

      • 1_CLUSTER

        image.png

SIMULATION

  • 1_CLUSTER
    • HMNOC_1_CLUSTER_TB

image.png

  • 4_CLUSTER
    • HMNOC_4_CLUSTER_TB

image.png

Demo

Average Filter

image.png

Result

image.png

Reference

  1. {Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks,” ISCA, 2016.}
  2. {Y.-H. Chen, S. Member, T.-J. Yang, J. Emer, V. Sze, and S. Member, “Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices,” ISCA, 2019.}
  3. https://github.com/karthisugumar/CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2