Kashish121/Just_HacktoberFest

Verilog Adder and Multiplier

DISCLAIMER: This repository has been created for practice purpose Verilog adder and multiplier code for FPGA.

File module description: 📑

1. bit_serial_adder.v : 8 bit adder.
2. testbench.v : Testbench for 8 bit adder.
3. ass33.v : 6 bit multiplier.
4. ass33_tb.v : Testbench for 6 bit multiplier.

Contributors 🏆

Name 🎖️	Social Media 👋	GitHub
Anmol Harsh	🐦 Twitter 🎓 LinkedIn	@anmolharsh
Kashish	🐦 Twitter 🎓 LinkedIn	@Kashish121

See the contribution graph here.