Pinned Repositories
Automatic-testbench-Generator
Automatic testbench generator was developed with intention to reduce the amount time and effort to generate testbench by reducing the amount of hard coding needed to generate testbench. Automatic testbench tool is able to use the VHDL design file and user input parameters to generate testbench successfully. Furthermore, with addition of GUI, the tool is simple and user friendly which could potentially help people with little to no prior knowledge about VHDL to learn about VHDL.
ConsoleApp1
First Repository
Kenneth-Tan-Kai-Xian's Repositories
Kenneth-Tan-Kai-Xian/Automatic-testbench-Generator
Automatic testbench generator was developed with intention to reduce the amount time and effort to generate testbench by reducing the amount of hard coding needed to generate testbench. Automatic testbench tool is able to use the VHDL design file and user input parameters to generate testbench successfully. Furthermore, with addition of GUI, the tool is simple and user friendly which could potentially help people with little to no prior knowledge about VHDL to learn about VHDL.
Kenneth-Tan-Kai-Xian/ConsoleApp1
First Repository