Repository for documentation purposes of our project in the ETHZ course EEAIC, edition 2022.
We implemented the paper from Faroni et al. [1] to implement a Class-D VCO as part of a whole PLL. Overall , we achieved a FoM @ 10 MHz of -190.14 dBc/Hz, with a total power budget of less than 4mW and a reference clock of 31.25MHz.
[1] L. Fanori and P. Andreani, "Class-D CMOS Oscillators," in IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3105-3119, Dec. 2013, doi: 10.1109/JSSC.2013.2271531.