Khaled-Pr/BCD_Counter
This design is for a BCD counter, that its initial count is 5 when it reaches 9 it goes back to 0 (ex: one cycle is: 5-6-7-8-9-0-1-2-3-4)
Verilog
No issues in this repository yet.
This design is for a BCD counter, that its initial count is 5 when it reaches 9 it goes back to 0 (ex: one cycle is: 5-6-7-8-9-0-1-2-3-4)
Verilog
No issues in this repository yet.