I am a software engineer at Cadence Design Systems, Inc., working within the Pegasus Verification System team. I am interested in the realm of Electronic Design Automation (EDA), particularly in the domain of algorithmic thinking.
Before joining Cadence, I pursued my MSc in Computer Science from National Tsing Hua University (NTHU), and obtained my BSc in Computer Science and Information Engineering from Tamkang University (TKU) in Taiwan. During my graduate studies, I had the privilege of conducting research under the guidance of Prof. Tsung-Yi Ho and had the valuable opportunity to collaborate extensively with the Advanced Semiconductor Engineering (ASE) Group.
My motto is "Per Aspera Ad Astra," a sentiment that reflects my aspiration to triumph over every challenge that comes my way throughout my entire life journey.
<p><strong>Sep., 2024:</strong> <b>Paper Acceptance</b> <br>
Our paper "<a href="" style="text-decoration: none">Hybrid Detour Refinement Strategy for Package Substrate Routing</a>" is accepted to 2025 30th Asia and South Pacific Design Automation Conference (ASP-DAC).</p>
<p><strong>Jan., 2024:</strong> <b>Paper Acceptance</b> <br>
Our paper "Hybrid Refinement Strategy for Package Substrate Routing" is accepted to 2024 The 25th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI).</p>
<p><strong>Sep., 2023:</strong> <b>Job Commencement</b> <br>
I start my first job as a software engineer at <a href="https://www.cadence.com/en_US/home.html" target="_blank">Cadence Design Systems, Inc.</a>, Taiwan!</p>
<p><strong>Aug., 2023:</strong> <b>MSc Graduation</b> <br>
I completed my MSc in Computer Science from <a href="https://nthu-en.site.nthu.edu.tw/" target="_blank">National Tsing Hua University (NTHU)</a>.</p>
<p><strong>Nov., 2022:</strong> <b>Paper Acceptance</b> <br>
Our paper "<a href="https://ieeexplore.ieee.org/document/10195268" style="text-decoration: none">Deep Learning based Refinement for Package Substrate Routing</a>" is accepted to 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC).</p>
<p><strong>Sep., 2021:</strong> <b>MSc Admission</b> <br>
I commenced my MSc in Computer Science at <a href="https://nthu-en.site.nthu.edu.tw/" target="_blank">National Tsing Hua University (NTHU)</a>.</p>
<p><strong>Jun., 2021:</strong> <b>BSc Graduation</b> <br>
I completed my BSc in Computer Science and Information Engineering from <a href="https://english.tku.edu.tw/" target="_blank">Tamkang University (TKU)</a>.</p>
<p><strong>Sep., 2017:</strong> <b>BSc Admission</b> <br>
I commenced my BSc in Computer Science and Information Engineering at <a href="https://english.tku.edu.tw/" target="_blank">Tamkang University (TKU)</a>.</p>
Sep. 2023 - present
Software Engineer II
Pegasus Verification System, Cadence Design Systems, Inc., Taiwan
- Layout Versus Schematic (LVS) RC-mode:
- Implement newly netlist comparison algorithm (∼6x speedup, ∼80% memory reduction).
- Tsing Hua Emerging Technology Automation (THETA) Lab
- Advisor: Prof. Tsung-Yi Ho
- Research Focus: Electronic Design Automation (EDA), Artificial Intelligence (AI)
- Master Thesis: Hybrid Refinement Strategy for Package Substrate Routing
- Overall GPA: 3.86/4.30
- Independent Study: TRIP-2-GO ~ A Convenient Platform for Traveler ~
- Overall GPA: 3.96/4.00
Hybrid Detour Refinement Strategy for Package Substrate Routing
Ding-Hsun Lin, Tsubasa Koyama, Yu-Jen Chen, Keng-Tuan Chang, Chih-Yi Huang, Chen-Chao Wang, and Tsung-Yi Ho
30th Asia and South Pacific Design Automation Conference (ASP-DAC), 2025
Abstract
Not prepared yet
**Hybrid Refinement Strategy for Package Substrate Routing** **Tsubasa Koyama**, Ding-Hsun Lin, Yu-Jen Chen, Keng-Tuan Chang, Chih-Yi Huang, Chen-Chao Wang, and Tsung-Yi Ho *The 25th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), 2024*
Deep Learning based Refinement for Package Substrate Routing
Peng-Tai Huang, Tsubasa Koyama, Keng-Tuan Chang, Chih-Yi Huang, Chen-Chao Wang, and Tsung-Yi Ho
IEEE 73rd Electronic Components and Technology Conference (ECTC), 2023
Abstract
Heterogeneous integration packaging has become increasingly important due to recent rapid technological advancements. In these designs, substrate routing is a critical factor in terms of time to market. While there are some existing works and automatic routing tools available to help designers solve routing problems, they often result in poor performance due to the complex constraints and specifications of industrial designs. Manual revision of these results is time-consuming and can take weeks. In this work, we propose a deep learning approach to improving the area distribution and reducing detours in the autorouting results of industrial Flip-Chip Ball Grid Array (FCBGA) substrate designs, with the goal of reducing the time needed for manual modification. Experimental results show that our proposed methods can effectively refine both detours and area distribution in auto-routing results, producing results that are similar to manual routing. We also successfully reduce the modification time compared to manual one.
Sep. 2021 - Jan. 2022, Teaching Assistant
11110CS 312000 Introduction of Integrated Circuit Design
National Tsing Hua University, Hsinchu
- Playing Sports (Volleyball
, Badminton 
, etc.) - Playing Board Games
- Going to Karaoke
- Listening to Music
- Watching Anime
- Reading Light Novels
- Email: a0918050152@gmail.com
- LinkedIn: linkedin.com/in/ktsubasa0304
- Facebook: fb.com/ktsubasa0304
- GitHub: github.com/Koyama-Tsubasa