Kyungsang

Kyungsang's Stars

• Intensivate/learning-journey

  Chisel Learning Journey

  Language:Jupyter Notebook10817

• cnrv/rocket-chip-read

  Comment on the rocket-chip source code

  17843

• zachjs/sv2v

  SystemVerilog to Verilog conversion

  Language:Haskell61058

• nturley/netlistsvg

  draws an SVG schematic from a JSON netlist

  Language:JavaScript67889

• logic-ng/LogicNG

  The Next Generation Logic Library

  Language:Java14026

• steveicarus/iverilog

  Icarus Verilog

  Language:C++3k547

• YosysHQ/sby

  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

  Language:Python43880

• enjoy-digital/litedram

  Small footprint and configurable DRAM core

  Language:Python402125

• m-labs/migen

  A Python toolbox for building complex digital hardware

  Language:Python1.3k214

• berkeley-abc/abc

  ABC: System for Sequential Logic Synthesis and Formal Verification

  Language:C967614

• MikePopoloski/slang

  SystemVerilog compiler and language services

  Language:C++707151

• pysmt/pysmt

  pySMT: A library for SMT formulae manipulation and solving

  Language:Python587135

• pymtl/pymtl3

  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

  Language:Python40950

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog3.4k807

• bogdanvuk/pygears

  HW Design: A Functional Approach

  Language:Python14513

• phanrahan/magma

  magma circuits

  Language:Python25925

• msoeken/cirkit

  A circuit toolkit

  Language:C++10038

• Nic30/hdlConvertor

  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

  Language:C++28972

• cristian-mattarei/CoSA

  CoreIR Symbolic Analyzer

  Language:Python7017

• f4pga/prjxray-db

  Project X-Ray Database: XC7 Series

  Language:Shell6635

• YosysHQ/arachne-pnr

  Place and route tool for FPGAs

  Language:C++41972

• rdaly525/coreir

  Language:C++10225

• masc-ucsc/livehd

  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

  Language:FIRRTL22049

• tree-sitter/tree-sitter

  An incremental parsing system for programming tools

  Language:Rust20.1k1.7k

• vmware-archive/cascade

  A Just-In-Time Compiler for Verilog from VMware Research

  Language:C++44344

• drom/awesome-hdl

  Hardware Description Languages

  1k97

• sqlalchemy/mako

  Mako Templates for Python

  Language:Python38564

• aolofsson/oh

  Verilog library for ASIC and FPGA designers

  Language:Verilog1.3k293

• jmahler/mips-cpu

  MIPS CPU implemented in Verilog

  Language:Verilog598186

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.3k298