/Fractional-Order-FIR-Lagrange

UESTC-分数阶时延FIR滤波器

Primary LanguageVerilog

Variable Fractional Delay FIR Digital Filter Design and Implementation on FPGA

filter design and fixed point simulate can be found in "Matlab". FPGA design by Quartus II can be found in "Quartus" hardware logic simulate by Modelsim can be found in "Modelsim"