/Pianista-Digital-Logic-H-project

SUSTech Digital Logic(H) Class Project

Primary LanguageVerilog

Initilization of ROM in IP core.

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The coe file can be found in the same dir as readme.md. It looks like this:

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The coe file should be placed in certain dir. Refer to lab's slide:

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It is suggestive to follow slide's instructions to instantiate the IP core, and add the coe file to its path.

The final IP core be like:

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