Pinned Repositories
ai_and_memory_wall
AI and Memory Wall blog post
ARM-Full-system-simulation-GEM5
ChampSim-Ramulator
A simulator integrates ChampSim and Ramulator.
CLRDRAM
Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture.
CROW
Source code for the architectural and circuit-level simulators used for modeling the CROW
DRAM-Bender
DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art DDR4 modules of different form factors. Five prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf
DRAM-Datasheet-Survey
A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. This data and its analysis are described in the 2022 paper by Patel et al.: https://arxiv.org/abs/2204.10378
DRAMPower
Fast and accurate DRAM power and energy estimation tool
dvfs
MSci project on DVFS, energy savings, and scheduling in Assymetric Multicore Processors (AMPs), using the gem5 simulator.
ramulator
A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
LailaChitra's Repositories
LailaChitra/ramulator
A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
LailaChitra/ai_and_memory_wall
AI and Memory Wall blog post
LailaChitra/ARM-Full-system-simulation-GEM5
LailaChitra/ChampSim-Ramulator
A simulator integrates ChampSim and Ramulator.
LailaChitra/CLRDRAM
Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture.
LailaChitra/CROW
Source code for the architectural and circuit-level simulators used for modeling the CROW
LailaChitra/DRAM-Bender
DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art DDR4 modules of different form factors. Five prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf
LailaChitra/DRAM-Datasheet-Survey
A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. This data and its analysis are described in the 2022 paper by Patel et al.: https://arxiv.org/abs/2204.10378
LailaChitra/DRAMPower
Fast and accurate DRAM power and energy estimation tool
LailaChitra/dvfs
MSci project on DVFS, energy savings, and scheduling in Assymetric Multicore Processors (AMPs), using the gem5 simulator.
LailaChitra/GPGPUSim-Ramulator
The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used to produce some of the results in our SIGMETRICS 2019 paper: Ghose et al., "Demystifying Complex Workload-DRAM Interactions: An Experimental Study" at https://arxiv.org/pdf/1902.07609.pdf.
LailaChitra/MemBen
Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 paper: Ghose et al., "Demystifying Complex Workload-DRAM Interactions: An Experimental Study" at https://arxiv.org/pdf/1902.07609.pdf.
LailaChitra/MIMDRAM
Source code for the architectural simulator used for modeling the PUD system proposed in our HPCA 2024 paper `MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing''. Paper is at: https://arxiv.org/pdf/2402.19080.pdf
LailaChitra/ramulator-pim
A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combines a widely-used simulator for out-of-order and in-order processors (ZSim) with Ramulator, a DRAM simulator with memory models for DDRx, LPDDRx, GDDRx, WIOx, HBMx, and HMCx. Ramulator is described in the IEEE CAL
LailaChitra/ramulator2
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
LailaChitra/scarab
Joint HPS and ETH Repository to work towards open sourcing Scarab and Ramulator
LailaChitra/tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
LailaChitra/UHMEM
A cycle-accurate simulator that models a hybrid memory subsystem consisting of multiple memory technologies. Described in the CLUSTER 2017 paper by Li et al. (https://people.inf.ethz.ch/omutlu/pub/utility-based-hybrid-memory-management_cluster17.pdf)
LailaChitra/VAMPIRE
An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 paper by Ghose et al. (https://people.inf.ethz.ch/omutlu/pub/VAMPIRE-DRAM-power-characterization-and-modeling_sigmetrics18_pomacs18.pdf)